1. Field of the Invention
This invention relates to a liquid crystal display, and more particularly to a liquid crystal display panel having a driving circuit built therein.
2. Description of the Related Art
A liquid crystal display (LCD), typically used as a display device of a television or a computer, controls light transmittance of a liquid crystal using an electric field to display a picture. Typically, the LCD includes a liquid crystal display panel having liquid crystal cells arranged in a matrix and a driving circuit for driving the liquid crystal display panel.
Referring to FIG. 1, a related art LCD includes a liquid crystal display panel 13 having (m×n) liquid crystal cells Clc arranged in a matrix, m data lines D1 to Dm and n gate lines G1 to Gn intersecting each other, thin film transistors (TFT) provided at the intersections of the data and gate lines, a data driving circuit 11 for applying data signals to the data lines D1 to Dm, and a gate driving circuit 12 for applying scanning pulses sequentially to the gate lines G1 to Gn.
The liquid crystal display panel 13 is formed by joining a (TFT) substrate provided with a TFT array to a color filter substrate provided with a color filter array with having a liquid crystal layer therebetween. The data lines D1 to Dm and the gate lines G1 to Gn cross each other perpendicularly. The TFT provided at each intersection of the data and gate lines transfers the data voltage signal supplied via the data line to a pixel electrode of the liquid crystal cell Clc in response to a scanning pulse from the gate line. The color filter substrate is provided with a black matrix, a color filter, a common electrode, etc.
The liquid crystal cell Clc rotates the liquid crystal having a dielectric anisotropy by a potential difference between the data voltage supplied to the pixel electrode and a common voltage supplied via the common electrode. The rotation of the liquid crystal is utilized to control light transmittance. A polarizer having a perpendicular light axis is attached onto the TFT substrate. The color filter substrate of the liquid crystal display panel 13, and an alignment film for determining a free-tilt angle of the liquid crystal is further provided on the inner side surface coming in contact with the liquid crystal layer. Further, each liquid crystal cell Clc is provided with a storage capacitor Cst. The storage capacitor Cst is situated between the pixel electrode and the pre-stage gate line or between the pixel electrode and a common line (not shown), thereby maintaining the data voltage applied to the liquid crystal cell Clc.
The data driving circuit 11 converts input digital video data into analog data voltage signals using a gamma voltage and applies the converted analog data voltage signals to the data lines D1 to Dm.
The gate driving circuit 12 sequentially applies scanning pulses so as to activate the gate lines G1 to Gn. A horizontal line of the liquid crystal cells Clc activated by the scanning pulse is supplied with the data signals via the data lines D1 to Dm.
More specifically, as shown in FIG. 2, the related art gate driving circuit 12 includes a shift register having first to nth stages 36 connected in a cascade to sequentially supply the scanning pulses to the gate lines G1 to Gn. All stages 36 shown in FIG. 2 are supplied with a common clock signal CLK, a high-level voltage signal VDD and a low-level voltage signal VSS. The first stage is supplied with a start pulse signal Vst and all remaining subsequent stages take as input the output of the previous stage. The first stage outputs the scanning pulse to the first gate line G1 in response to the start pulse Vst and the clock signal CLK. The second to nth stages sequentially outputs the scanning pulses to the second to nth gate lines G2 to Gn in response to the output signal of the previous stage and the clock signal CLK. The first to nth stages have the same circuit configuration. Clock signals having different phases are used for the clock signal CLK.
FIG. 3 illustrates a detailed circuit configuration of the first stage 36 of the shift register 12 shown in FIG. 2. The first stage 36 includes an output buffer 38 outputting the scanning pulse to the gate line G1 under the control of the controller 37 (see also FIG. 5). The output buffer 38 includes a pull-up NMOS transistor NT6 and a pull-down transistor NT7. When turned on, the pull-up transistor NT6 transfers the first clock signal CLK1 to the output line. When turned on, the pull-down NMOS transistor NT7 transfers the low-level voltage signal VSS to the output line. The transistor NT6 turns on when the Q node (part of the controller 37) is high and the transistor NT7 turns on when the QB node is high (also part of the controller 37). The controller 37 includes first to fifth NMOS transistors NT1 to NT5 for controlling the Q node and the QB node, which in turn control the output of the output buffer 38 as noted above. The first stage 36 is supplied with the high-level and low-level voltages VDD and VSS, the start pulse Vst, and with clock signals CLK1 to CLK4. The clock signals CLK1 to CLK4 have different phases from each other as shown in FIG. 4.
Hereinafter, the operation of the first stage 36 will be described with reference to the driving waveform shown in FIG. 4. During period A, the start pulse Vst and the fourth clock signal CLK4 are driven high. As a result, the first and second NMOS transistors NT1 and NT2 are turned on to pre-charge the Q node high. The high voltage of the Q node turns on the pull-up NMOS transistor NT6 which in turn allows the low voltage of the first clock signal CLK1 to be output to the first gate line G1. Also during period A, the fifth NMOS transistor NT5 is turned on by the high voltage of the start pulse Vst, which in turn pulls the QB node low. Both the NMOS transistor NT3B and the pull-down NMOS transistor NT7 are turned off due to the low voltage applied the QB node. Because the third clock signal CLK 3 is low during period A, the NMOS transistors NT3A and NT4 also are turned off. The transistor NT3A being turned off prevents the Q node from being pulled-down low and the transistor NT4 being turned off prevents the QB node from being pulled-up high.
During period B, the first clock signal CLK1 is driven high while both the start pulse Vst and the fourth clock signal CLK4 are driven low. The low states of the start pulse Vst and the fourth clock signal CLK4 cause the first and second NMOS transistors NT1 and NT2 to turn off. The pull-up NMOS transistor NT6 remains on due to the floating high voltage at the Q node. During period B, because of the high voltage of the first clock signal CLK1, the Q node is bootstrapped due to a parasitic capacitor CGD formed by an overlap between the gate electrode and the drain electrode of the pull-up NMOS transistor NT6. As a result, the Q node voltage is raised even higher which ensures that the pull-up NMOS transistor NT6 remains on. The high voltage of the first clock signal CLK1 is transferred to the output line of the output buffer 38 and appears as a scanning pulse to activate the first gate line G1.
During period C, the first clock signal CLK1 is driven low and the second clock signal CLK2 is driven high. The start pulse Vst and the fourth clock signal CLK 4 remain low. The first and second NMOS transistors NT1 and NT2 remain turned off due to the low voltages of the start pulse Vst and the fourth clock signal CLK4. The Q node remains in a floating high state to maintain the pull-up NMOS transistor NT6 in an on state. Thus, the low voltage of the first clock signal CLK1 is outputted to the first gate line G1 to deactivate the gate line G1.
During period D, the second clock signal CLK2 is driven low and the third clock signal CLK3 is driven high. The high state of the third clock signal CLK3 turns on the NMOS transistors NT3A to pull the Q node down low by the low voltage VSS. The transistor NT4 is also turned on due to the high voltage of the third clock signal CLK3. When the transistor NT4 is turned on, the QB node is pulled up high by the high voltage VDD. The high voltage at the QB node turns on the NMOS transistor NT3B to fully discharge the Q node. The pull-down NMOS transistor NT7 also turns on to output low voltage VSS to the first gate line G1.
During period E, the fourth clock signal CLK4 is driven high while the start pulse Vst remains low. Also the third clock signal CLK3 is driven low. The fourth transistor NT4 is turned off due to the third clock signal CLK3 being driven low and the fifth transistor NT5 remains turned off due to the low voltage of the start pulse Vst remaining low. As a result, the QB node is floated high. Thus, the pull-down NMOS transistor N7 remains on to maintain the low voltage VSS to the first gate line G1. The pull-down NMOS transistor NT7 remains on to supply the first gate line G1 with the low voltage VSS until the start pulse Vst is driven high.
If the related art gate driving circuit as mentioned above is built into a liquid crystal display panel 10 as shown in FIG. 5 by utilizing an amorphous silicon TFT, then the size of the output buffer 38 of each stage 36, that is, the pull-up and pull-down NMOS transistors NT6 and NT7 is significantly large. This because the scanning pulse is directly applied via the output buffer 38 as described above and the channel width of the output buffer 38 has a large affect on the life of the liquid crystal display panel 10. According to a design, the output buffer 38 must keep a channel width of more than several thousand μm. For this reason, an area occupied by the gate driving circuit 30 is substantial. However, certain product standards impose limits in how much the circuit area within the non-display area can be increased.
Referring to FIG. 5, the gate driving circuit 30 is provided in a non-display area of the display panel 10 and positioned at an outer portion of the display panel 10. A sealant 32 for joining the TFT substrate with the color filter substrate is coated, along a peripheral portion of the circuit area provided with the gate driving circuit 30, onto the non-display area. In FIG. 5, a makeup of a representative stage, such as the first stage 36 of FIG. 2, is illustrated. As illustrated, a line on glass (LOG) area 34, which is provided with a plurality of LOG-type signal lines for supplying a plurality of clock signals and power signals, is located on the left side of the stage 36, and the sealant 32 is provided on the left side of the LOG area 34. The stage 36 includes the output buffer 38 made up of the pull-up and pull-down transistors NT6 and NT7, and the controller 37 made up of the first to fifth transistors NT1 to NT5 for controlling the output buffer 38.
In the related art, if a glass fiber included in the sealant 32 comes in contact with a metal, then a damage can occur to cause an open such that the gate driving circuit 30 cannot be formed in a manner to overlap with the sealant 32. As shown in FIG. 6, a contact electrode 50 is formed to contact a gate metal layer 42. The contact electrode 50 also makes contact with the source/drain metal layer 42. The source/drain metal layer 46 is formed in a different layer than the gate metal layer 42 and a gate insulating film 44 is provided therebetween, all on a substrate 40. The exposed structure as shown in FIG. 6 for each stage 36 included in the gate driving circuit 30.
Referring to FIG. 6, the contact electrode 50 connects the gate metal layer 42 exposed via a first contact hole 52 passing through the protective film 48 and the gate insulating film 44 to the source/drain metal layer 46 exposed via a second contact hole 54 also passing through the protective film 48. For instance, in the detailed circuit of one stage shown in FIG. 3, the contact electrode 50 is utilized to connect the first to sixth nodes N1 to N6 to supply lines for high-level and low-level voltages VDD and VSS, supply lines for first to fourth clock signals CLK1 to CLK4 and a supply line for start pulse Vst, respectively, a connection node N7 between the gate electrode and the source electrode of the first transistor NT1, the Q node and the QB node, etc. If the contact electrode 50 comes in contact with the glass fiber 56 included in the sealant 32, then the contact electrode 50 may corrode to cause an electrical open.
Referring back to FIG. 5, the gate driving circuit 30 is not overlapped with the sealant 32. As a result, the circuit area is reduced. For example, in the case of 2.2″ QVGA, a line width of the non-display area extended from the display area (pixel area) 20 until a scribing line of the thin film transistor substrate is about 2.2 mm. With such non-display area, the sealant 32 occupies a line width of 0.6 mm. Thus, a line width of the circuit area in which a usable gate driving circuit 30 can be formed must be within about 0.8 □0.9 mm in consideration of a margin required for the LOG area 34. Since the size of the output buffer 38, which is preferred to be large, is set within the circuit area and limited as described above, a scheme to increase the circuit area is sought.